As dynamic random access memory (DRAM) devices become more highly integrated, the space available for each memory cell is reduced. Accordingly, three-dimensional memory cell capacitor structures have been developed to provide a desired capacitance on a reduced surface area. Accordingly, a memory cell may have a height over the substrate of 1 .mu.m or higher. This height, however, may result in a substantial step difference between a cell array region of the DRAM and a peripheral circuit region of the DRAM. Irregular reflections may thus occur in subsequent photolithography steps thereby reducing the exposure resolution.
Accordingly, interdielectric layers providing high degrees of planarization are desired. For example, an interdielectric layer can be formed from a layer of borophosphosilicate glass (BPSG), and the borophosphosilicate glass layer can be reflowed to provide a planar surface. Alternately, an interdielectric layer can be formed from a layer of 03-tetraethyl orthosilicate undoped silicate class (03-TEOS USG), and this layer can be etched back to provide a planar surface.
When reflowing a BPSG layer, however, the DRAM may be heated to a temperature of 850.degree. C. for 30 minutes or longer. In DRAMs with a capacity of 256 Mb or higher, TaO or BST may be used to provide the capacitor dielectric layers, and a high temperature reflow step may damage these dielectric layers. Accordingly, it may be desirable to avoid the high temperature reflow step. The etch back used to planarize a layer of 03-TEOS USG may result in relatively complicated processing steps. In addition, the BPSG and 03-TEOS USG layers may be unable to provide sufficient planarization.
In response, spin-on-glass (SOG) layers have been used to provide planarized interdielectric layers. Spin-on-glass layers can be used to provide a high degree of planarization without requiring complex processing steps or high temperature steps. When using a layer of a spin-on-glass as an interdielectric layer, however, the wet etch rate and the hygroscopicity of the spin-on-glass layer should be reduced using a heat treatment. In particular, a wet etch may be used to remove a native oxide layer when depositing a conductive layer after forming a contact hole through the spin-on-glass layer. If the wet etch rate of the spin-on-glass layer is too high, the size of the contact hole may increase excessively. Furthermore, if the hygroscopicity of the spin-on-glass layer is too high, the dielectric constant of the spin-on-glass layer may be too high thereby resulting in malfunctions for the DRAM device.
A capping layer on the spin-on-glass layer can be used to reduce the absorption of moisture into the spin-on-glass layer thereby reducing problems relating to hygroscopicity. The spin-on-glass layer is thus formed on the substrate, the memory cell access transistor, and the bit line, and the spin-on-glass layer is baked at a temperature of 750.degree. C. or less. A capping layer is then formed on the spin-on-glass layer to reduce the absorption of water into the spin-on-glass layer. The step of baking the spin-on-glass layer evaporates solvents from the spin-on-glass layer thereby leaving a solid layer having properties similar to those of SiO.sub.2. The resulting structure including the spin-on-glass layer and the capping layer can then be annealed at a temperature of 550.degree. C. or higher.
The wet etch rate of the spin-on-glass layer, however, may be higher than that of the capping layer. When forming contact holes through the capping layer and the spin-on-glass layer, the profiles of the resulting contact holes may thus be degraded. In particular, a wet etch used to form the contact holes may undercut the capping layer adjacent the contact hole because of the difference in etch rates. Accordingly, voids may result when depositing a conductive via in the contact hole.
In particular, an oxide layer formed by plasma enhanced chemical vapor deposition (PECVD) can be used to form the capping layer, and this oxide layer may have a lower etch rate than a spin-on-glass layer. Accordingly, when etching contact holes through the capping layer and the spin-on-glass layer, the etch may undercut the capping layer so that protruding edge portions of the capping layer extend beyond the spin-on-glass layer adjacent the contact hole. As discussed above, voids may thus result when forming a conductive via in the contact hole.
Accordingly, there continues to exist a need in the art for improved methods for forming contact holes for semiconductor devices.